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45 LCP - Center Error LPF pin
46 SCLK I Serial Clock
47 SDATA I/O Serial Data
48 SDEN I Serial Data Enable
49 HOLD1 I Hold Control
50 VNA - Ground
51,52 FNP,FNN O Differential Normal Output
53,54 DIP,DIN I Analog inputs for RF Single Buffer
55 RX - Reference Resistor Input
56 BYP I/O
57 SIGO O Single Ended Normal Output
58 VPA - Power
59,60 AIP,AIN I AGC Amplifier Inputs
61,62 ATOP/ATON O Differential Attenuator Output
63 CDRF I RF Signal Input
64 CDRFDC O CD RF signal Output
1-22
16-1
33-48
TH-A30
M12L64164A (AU13, AU14) : SDRAM
1.Pin layout 2.Pin function
VDD 1 54 VSS
Symbol Function
DQ0 2 53 DQ15
CLK System Clock
VDDQ 3 52 VSSQ
DQ1 4 51 DQ14 CS Chip Select
DQ2 5 50 DQ13
CKE Clock Enable
VSSQ 6 49 VDDQ
A0 ~ A11 Address
DQ3 7 48 DQ12
DQ4 8 47 DQ11
A12 , A13 Bank Select Address
VDDQ 9 46 VSSQ
RAS Row Address Strobe
DQ5 10 45 DQ10
DQ6 11 44 DQ9 CAS Column Address Strobe
VSSQ 12 43 VDDQ
WE Write Enable
DQ7 13 42 DQ8
L(U)DQM Data Input / Output Mask
VDD 14 41 VSS
LDQM 15 40 NC
DQ0 ~ DQ15 Data Input / Output
WE 16 39 UDQM
VDD / VSS Power Supply / Ground
CAS 17 38 CLK
RAS 18 37 CKE VDDQ / VSSQ Data Output Power / Ground
CS 19 36 NC
NC No Connection
A13 20 35 A11
A12 21 34 A9
A10/AP 22 33 A8
A0 23 32 A7
A1 24 31 A6
A2 25 30 A5
A3 26 29 A4
VDD 27 28 VSS
3.Block diagram
CLK
Clock
Generator
Bank D
CKE
Bank C
Bank B
Row
Address
Address
Buffer
Mode Bank A
&
Register
Refresh
Counter
Sense Amplifier
L(U)DQM
Column
Column Decoder
CS
Address
Buffer
RAS
&
Refresh
CAS
Counter
Data Control Circuit
DQ
WE
1-23
Row Decoder
Control Logic
Buffer
Command Decoder
Latch Circuit
Input & Output
TH-A30
BA4560 (AIC2, IC5, IC6, IC7, U1, U3, U5, U9, U13) : Dual op amp.
1.Pin layout
OUT1 1 8 VCC
IN1 2 7 OUT2
1ch
+
2ch
+ IN1 3 6 IN2
+
VEE 4 5 + IN2
74LVT573 (U10, U11, U12) : Latch
1. Pin layout 2. Pin function 3. Truth table
Symbol Function
Inputs Outputs
OE 1 20 Vcc
D0 2 19 O0
D0-D7 Data Inputs
LE OE Dn On
D1 3 18 O1
LE Latch Enable Input
X H X Z
D2 4 17 O2
D3 5 16 O3
OE Output Enable Input H L L L
D4 6 15 O4
H L H H
O0-O7 3-STATE Latch Outputs
D5 7 14 O5
L L X O0
D6 8 13 O6
H:HIGH Voltage Level
D7 9 12 O7
L:LOW Voltage Level
GND 10 11 LE Z:High Impedance
X:Immaterial
O0:Previous O0 before HIGH to LOW transition of Latch Enable
FAN8082 (U10) : DC motor driver
2. Block diagram
1.Pin layout
1 8
DRIVER OUT
GND 1 8 VO2 GND V
O2
V
O1 2
7
VO1 2 7 PVCC PV
CC
PRE DRIVER
VCTL 3
6
SV
VCTL 3 5 SVCC CC
TSD BIAS
VIN1 4 LOGIC SWITCH
5
V
IN2
VIN1 4 6 VIN2
3. Pin function
Pin No. Symbol I/O Function
1-
GND
Ground
2V O Output 1
O1
3V I Motor speed control
CTL
4VIN1 I Input 1
5VI Input 2
IN2
6SV- Supply voltage (Signal)
CC
7PVCC - Supply voltage (Power)
8V O Output 2
O2
1-24
TH-A30
74HCT245 (U15) : Transceiver
1.Pin layout 2.Truth table
ENABLE
Control
Vcc G B1 B2 B3 B4 B5 B6 B7 B8
Operation
Inputs
20 19 18 17 16 15 14 13 12 11
G DIR 245
L L B data to A bus
L H A data to B bus
H X
isolation
H = HIGH Level
L = LOW Level
X = Irrelevant
1 2 3 4 5 6 7 8 9 10
DIR A1 A2 A3 A4 A5 A6 A7 A8 GND
M5705 (DU3) : DVD-ROM controller
1.Block diagram
4M DRAM
M5703/M5707
RF
ATAPI
Amp
&
Data
PC
M
MPEG
Separator
RAM
DVD-DSP I/F
Arbiter
MPEG
DEC.
C3 ECC
EDC
Digital
Motor
CD-DSP
Servo
Target MCU
Driver
Search
ROM
1-25
TH-A30
BA7612F (VIC3) : Video signal switcher
1. Block diagram
2. Truth table
CTL A CTL B OUT
IN1 1 8 VOUT
MUTE
L (OPEN) L (OPEN) IN1
6dB 75&!
CTLA 2 7 VCC
L (OPEN) HIN2
CTLB 3 LOGIC 6 IN3
HIN3
L (OPEN)
HH MUTE
IN2 4 5 GND
TDA7440D (U2) : Audio processor
1. Terminal layout 2. Block diagram
MUXO-L IN(L) TRE(L) BIN(L) BOUT(L)
4 8 9 18 14 15
LIN1
RIN3 1 28 RIN4
100K
RB
RIN2 2 27 LOUT
5
RIN1 3 26 ROUT
LIN2
LIN1 4 25 AGND 100K
27
LIN2 5 24 VS SPKR ATT
6 G VOLUME TREBLE BASS LOUT
LEFT
LIN3
LIN3 6 23 CREF
100K
LIN4 7 22 SDA
7
MUXO-L 8 21 SCL
LIN4
IN(L) 9 20 DGND
100K
21
0/30dB SCL
MUXO-R 10 19 TRE(R)
I2CBUS DECODER + LATCHES 22
2dB STEP
3 SDA
IN(R) 11 18 TRE(L)
RIN1 20
DGND
BIN(R) 12 17 PS1 100K
BOUT(R) 13 16 LP
2
RIN2
BIN(L) 14 15 BOUT(L)
100K 26
SPKR ATT
G VOLUME TREBLE BASS ROUT
RIGHT
1
RIN3
VREF
100K
24
28 VS
RIN4 SUPPLY 25
INPUT MULTIPLEXER AGND
RB
100K
+ GAIN
10 11 19 12 13 23
MUXO-R IN(R) TRE(R) BIN(R) BOUT(R) CREF
W29EE512 (DU5) : Flash memory
1. Pin layout 2. Block diagram
3. Pin function
VDD
Symbol Function
Vss
4 3 2 1 32 31 30
A0~A15 Address input
A7 5 29 A14
DQ0~DQ7 Data I/O
A6 6 28 A13
DQ0
A5 7 27 A8
CS CE Chip enable
OUTPUT
CONTROL
A4 8 26 A9
OE
OE Output enable
BUFFER
A3 9 25 A11
WE DQ7
A2 10 24 OE
WE Write enable
A1 11 23 A10
Vcc Power
A0 12 22 CE
DQ0 13 21 DQ7 GND Ground
A0
14 15 16 17 18 19 20
NC No connect
CORE
DECODER
ARRY
A15
1-26
A12
A15
NC
NC
Vcc
WE
NC
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
GND
TH-A30
TDA7449L (U7, U12) : Audio processor
1.Pin layout 2.Block diagram
MUXOUTL
10
CREF 1 20 SDA
8
L-IN1
VS 2 19 SCL
100K
PGND 3 18 DIG_GND
ROUT 4 17 N.C.
9
L-IN2 5
LOUT 5 16 N.C. SPKR ATT
G VOLUME LOUT
LEFT
100K
R_IN2 6 15 N.C.
R_IN1 7 14 N.C.
L_IN1 8 13 N.C.
19
0/30dB SCL
L_IN2 9 12 N.C.
7 I2CBUS DECODER + LATCHES 20
2dB STEP
R-IN1 SDA
MUXOUT(L) 10 11 MUXOUT(R)
18
100K DIG_GND
6
R-IN2 4
SPKR ATT
G VOLUME ROUT
RIGHT
100K
VREF
2
VS
SUPPLY 3
INPUT MULTIPLEXER AGND
+ GAIN
11 1
D98AU868
MUXOUTR CREF
TL3472 (RU2) : Op. amp.
1.Pin layout
1OUT 1 8 VCC+
1IN± 2 7 2OUT
1IN+ 3 6 2IN±
VCC±/GND 4 5 2IN+
1-27
TH-A30
VICTOR COMPANY OF JAPAN, LIMITED
AUDIO & COMMUNICATION BUSINESS DIVISION
PERSONAL & MOBILE NETWORK BUSINESS UNIT. 10-1,1chome,Ohwatari-machi,Maebashi-city,371-8543,Japan
200208
(No.21128)
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